Advanced Arduino Assembly – Review Material

Advanced Arduino Assembly

Class Lectures Labs 3Dot PaperBot Programming Problems Review Material Reference Sheets

Quiz #1 Review

Note: Answers are listed after each question but, for the best study experience always answer them on your own first.

With respect to the functional layout of data and program memory, which architecture, Charles Babbage’s mechanical Analytical Engine designed in 1833 or Dr. John Von Neumann’s electronic EDVAC computer designed over 100 years later in 1943, most closely resemble the AVR and why?

See Answer

The Analytical Engine designed in 1833 and the EDVAC designed in 1943 have the same five (5) principle organs that make up all modern day computers (Control, ALU, Memory, Input, and Output). Functionally, the main difference, other than the names given to each organ by Charles Babbage and Dr. Von Neumann, is the way data and instructions are stored. The Analytical Engine has a separate set of punched cards for data and the program. In contrast, both data and programs are stored together within the EDVAC’s ultrasonic delay line memory. Like the Analytical Engine, the AVR architecture separates Flash program and SRAM data memory and therefore is more like the Analytical Engine. Today this is known as the Harvard Memory Model.

2. What is the address of the last byte in memory of a computer system with an 18-bit address bus and an 8-bit data bus?

See Answer

$2^{18} – 1 = 262,143_{10}$

Range of addresses is $00000_{16}$ to $3FFFF_{16}$

3. What is the maximum number of characters that can be represented by an 8-bit code?

See Answer

$2^{n-1} = 2^8 = 256$ characters

4. What is the largest unsigned number, in decimal, that can be held in an 8-bit register?

See Answer

$2^8 - 1= 255_{10}$

5. What is the range of signed 2’s complement numbers, in decimal, that can be held in an 8-bit register?

See Answer

$-2^{n-1} \cent$ $2^{n-1}-1=-128_{10}$ to $127_{10}$

6. Convert $35_{10}$ to binary and hex.

See Answer

$16| 35_{10}}$ $-2$ x $16=3$

$16|2$ $-0$ x $16=2$ $\rightarrow 23_{16}=100011_2$

$0$

7. Convert $35_{16}$ to decimal.

See Answer

$3$ x $16^1 =48$

$5$ x $16^0=5$

$48+5=53_{10}$

8. Perform the hex subtraction 36Bh – F6h.

See Answer

$36B_{16}$

$\frac{-F6_{16}}{275_{16}}$

9. Applying DeMorgan’s Theorem and the Basic Laws and Theorems of Boolean Algebra; simplify the following expressions:

$\overline{\overline{a}+bc}$

$\overline{\overline{a}+\overline{b}}$

See Answer

$\overline{\overline{a}+bc}$ = $a(\overline{b}+\overline{c})$

$\overline{\overline{a}+\overline{b}}$ = $a\cdot b$

10. Complete the timing diagram for the following edge triggered D Flip-Flop. Q is initially at logic $0$ .

See Answer

11. Assuming a 64-bit computer, for example the Intel Itanium microprocessor; place the following terms in ascending order relative to the number of binary digits they represent (Nibble, Word, Bit and Byte).

See Answer

Bit, Nibble (4 bits), Byte (8 bits), Word (64 bit architecture)

12. Which register in a CPU always contains an address?

What address is contained in this register?

See Answer

Program Counter (PC).

The program counter holds the address of the next instruction to be executed.

13. During an opcode fetch, what is the information on the address and data buses?

What is the direction of information flow on these buses during an opcode fetch?

See Answer

The address bus contains the address of the next instruction to be executed (i.e. the contents of the program counter). The data bus then contains the actual instruction (i.e. the opcode) fetched from memory.

14. The sole purpose in life of a computer is to do what?

See Answer

The sole purpose in life of a computer is to fetch and execute instructions.

15. The Arduino Uno Board uses the Atmel Atmega328P microcontroller. Use the web to complete the following table.

Feature	ATtiny24	ATmega328P	ATmega644P
Flash Program Memory
SRAM Data Memory
EEPROM
Timers (8 and 16 bit)
I/O pins
Serial peropherals (UART, USART, USI, SPI)
10-bit A/D channels

See Answer

Feature	ATtiny24	ATmega328P	ATmega644P
Flash Program Memory	2KBytes	32KBytes	64Kbytes
SRAM Data Memory	128 Bytes	2 KBytes	4 KBytes
EEPROM	128	1 KBytes	2 KBytes
Timers (8 and 16 bit)	2	3	3
I/O pins	12	23	32
Serial peropherals (UART, USART, USI, SPI)	2	2	3
10-bit A/D channels	8	8	8

AVR Assembly Language Programming

16. List all AVR ISA (Instruction Set Architecture) registers.

See Answer

Program Counter (PC)

General Purpose Registers R0 thru R31 Status Register (SREG)

Stack Pointer (SP)

17. For the three addressing modes listed, indicate where the data is located and at what address.

Addressing Mode	Data is located here	ATmega328P Address Space
Register
Immediate
Direct

See Answer

Addressing Mode	Data is located here	ATmega328P Address Space
Register	CPU	00₁₆ – 1F₁₆ (R0 – R31)
Immediate	Flash Program Memory	0000₁₆ – 03FF₁₆
Direct	SRAM Data Memory I/O	0000₁₆ to 08FF₁₆ 0000₁₆ to 003F₁₆

Quiz 2 Sample

EE346A Quiz #2 Name ___________________

Key ______

Frequency _____ Hz

Clock Frequency: 8MHz, 10MHz, 16MHz, 20MHz

Timer: T0, T1, T2, Custom ____ (default 12 bits)

IMPOTANT: Please read before you begin:

Unless otherwise directed (see question 8), please provide base 10 answers using decimal notation (no powers of 2 or fractions 1/3). If not a whole number, you can limit written answers to three places past the decimal point. Please round up or down as needed (round 5 up). For example 62.4875 would be written as 62.488.
Prefix hexadecimal digits using 0x notation.
To avoid round-off errors later in the quiz, use the memory function on your calculator to save the answer to earlier (dependent) question.
Always check your answers. When possible turn your answer into a question. For example, take your answer to question 9 and convert to a decimal number, the answer to question 8, to verify that conversion is correct. Using this approach you can also verify your answers to questions 6, 4, and 7.

	Question	Answer	Units
1	How many bits is the Timer/Counter		bits
2	Assuming the counter is cleared (equal to 0), How many tics of the clock have occurred at the moment the overflow bit is set (for example for Timer 1 overflow bit is TOV1)?		tics
3	What is the period of the waveform?		msec
4	Assuming a 50% duty cycle, what delay should be programmed into the Timer/Counter?		msec
5	What clock prescalar should be selected (1, 8, 64, 256, and 1024)?
6	Assuming this prescalar value, how many microseconds does it take for 1 tic of the clock?		µsec
7	What is the maximum delay that can be generated by this delay?		msec
8	What whole number (positive interger) should be preloaded into the Timer/Counter register(s) to generate the desired delay in decimal?		Base 10
9	What value should be preloaded into the Timer/Counter register(s) to generate the desired delay in hexadecimal?		Base 16
10	What assembly instruction opcode mnemonic (do not include operands) would you use to load this constant into register r16?

Show all your work here and on the back of this page.

Quiz 3 Study Guide

While I always hope to cover all the material and examples in the lecture material, I typically run out of time before material. Here are some of the lectures where you can find problems and examples you can work on at home.

Lecture 01 to 09 Programming and Lab Basics (Load-Store, SREG, Branching and Looping, Subroutines, GPIO)
Lectures 10 to 12 Interrupts , for example lecture 11 page 15 “Practice Problems”
Lecture 13 AVR Indirect Addressing Modes – pages 11 and 16 Program Examples
Lecture 14 AVR Logic and Shift – Page 5 Knight Rider, examples in slides, and Questions page 14
Lecture 15 AVR Stack Operations – Review example on page 6

You can find review question in the AVR Final Review document under the corresponding lecture headings.

Lecture 01 to 09 Programming and Lab Basics

Given two numbers, calculate the difference, signed and unsigned relationship.
For a given arithmetic operation (add or subtract) define the state of SREG bits H, S, V, N, Z, C.
Know how to simulate a call to ReadSwitches.
Know how to save and restore the Status Register (SREG)
Know the methods for sending information to and from a subroutine.
Be prepared to write a program to send data to and receive data from a subroutine. Specifically, in a register or one of the SREG bits. Your program will not be required to implement a stack frame.
Be able to identify code which violates one or more of the rules for working with a subroutine or an interrupt service routine. For example the code jumps out of a subroutine, a push is not matched to a pop instruction, or a ret instruction is used to end an ISR.

Lecture 10 to 12 – Interrupts

Understand how an ISR is different from and similar to a subroutine.
Be able to locate interrupts within the Interrupt Vector Table (IVT) and the priority of each.
Know how to configure an interrupt to be triggered based on the nature of the input signal (low logic level, logic change, falling or rising edge.
Know how to enable a given external interrupt(s). This external interrupt(s) might be one of our two dedicated external interrupt lines or one or more of our pin-change interrupt lines.
Know what happens when an interrupt is triggered and what if any registers are placed on the stack.
Given our ground bounce (low-pass filter) circuit be able to generate the output for a given clock a button input condition.

Lecture 13 – Indirect Addressing Mode

What does defining a table actually do? Does it give addresses for constants that already exist in program memory or does it do something else?
What is an index and why is it used?
If the least significant bit selects whether ZL or ZH is used, is one of them (ZL or ZH) a 7 bit register?
Do the mnemonics “low” and “high” automatically correspond to the low and high bytes of the Z-register?
Specifically for lab 10, why is the index equal to 20*row+col?
What register pair is found in the source operand address field of an lpm instruction?
What register numbers correspond to pre-defined mnemonics ZH:ZL?

Lecture 14 – Indirect Addressing Mode

Be able to clear, set, and toggle bits, including setting a bit pattern (see page 12)
Know how to test if one or more bits are set or cleared.
Understand multiplication and division by 2 using shift instructions.

Lecture 15 – AVR Stack Operations

Understand the difference between the difference between a LIFO and a FIFO stack
Understand the difference between an implicit and explicit stack operation.
Given the address of an rcall instruction, the address where the called subroutine begins, and the value of the stack pointer before the call; be prepared to calculate what the stack pointer will be equal to after the call instruction; at the beginning of the subroutine and the contents of the stack.
Be able to identify the code within a subroutine that will result in stack incoherence or a poorly formed series of pushes and pops.

Load-Store Worksheet

Load-Store Worksheet

As you work through the following questions, please have at hand your reference pages provided along with Midterm 1.

Question #1:

Computers at the most fundamental level manipulate data. This may be as simple as transferring the data from one place to another or executing an add operation. In a RISC architecture the data to be manipulated is contained in one or more general purpose registers within the central processing unit (CPU) of the microcontroller. These registers go by a number of names including temporary and scratch-pad. How many general purpose registers does our AVR processor have and how many bits wide is each?

Answer #1:

The AVR processor has 32 8-bit registers.

Loading Data

Question #2:

Another way of saying this is that all operations on the data are register-register. To get the data into the CPU we will need to “Load” it from somewhere. That somewhere can be from SRAM Data memory, Flash Program memory, an Input/Output register, or Extended Input/Output register.

I want to multiply a number in one of our registers by the constant 33₁₀. Where would you expect to find the number 33₁₀?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #2:

Constants are encoded with the program instruction, so the answer is Flash Program memory.

Question #3:

Looking at the “Register Summary” you can see that each of our three general purpose I/O ports (B, C and D) are defined by three registers (PORT, DD, and PIN). Notice that all of these registers have two addresses. The first number in the “Address” column, is the I/O address, the second (in parenthesis) is its duplicate address within the data memory address space. For now we will simply use the I/O address.

I want to read a temperature sensor, whose digital value is wired to one of our three general purpose digital I/O Ports. In what “address space” can you find this data?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory
Hint: Look at the “Register Summary” pages in the handout.

Answer #3:

All of our general purpose digital I/O ports are located in the I/O register address space. Specifically, I/O address 0x00 to 0x3F.

Question #4:

When the AVR processor was originally designed, the architects assumed that 64 I/O addresses (0x00 to 0x3F) would be sufficient for accessing all the peripheral devices co-located with the processor. When Atmel adopted the AVR processor as its core for the ATmega line of microcontrollers, they quickly discovered that they would need more than 64 I/O addresses. To accommodate the additional space they mapped these new “Extended” I/O registers into the SRAM address space of the ATmega and named it the Extended I/O address space. Looking at the register summary you can find these extended I/O registers starting at memory location 0x60 to 0xFF. This means that our actual SRAM data memory begins at address 0x0100.

With respect to the “Register Summary” table where would you find the registers used by the ATmega Analog-to-Digital Converter (ADC Data Registers).
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #4:

The result of an analog-to-digital conversion are located in registers ADC Data Register Low byte and ADC Data Register High Byte. These registers are located at Extended I/O address 0x78 and 0x79 respectively.

Question #5:

I want to load a variable named X, where would you expect to find this variable?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #5:

Variables which are located in SRAM data memory.

Question #6:

Where would I find an Array?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #6:

An array is simply an indexed set of variables, so they would be located in SRAM data memory.

Question #7:

I want to add an offset of 100₁₀ to each value in an array. Where would you expect to find the number 100₁₀ in my program?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #7:

Because I know I always want to add 100 – this is a constant that I would save in Flash Program memory. This number would be encoded with the instruction.

Question #8:

I want to load the value of the Watchdog Timer Control Register (WDTCSR). Where can I find this register?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #8:

Looking at the Register Summary, you will find WDTCSR in the Extended I/O address space of the ATmega. In this example, extended I/O address 0x60.

Question #9:

When the AVR processor executes an arithmetic instruction, like add, we often want to know more than simply the answer. For example; is the answer correct? Is the answer zero? These are some of the answers located in the Status Register (SREG). Where would you find this data?a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #9:

The status register is located in the I/O address space of the AVR processor at location 0x3F. Once again, if we are presented with both an I/O address 0x3F and a memory address (0x5F) we will classify the register as being within the I/O address space of the processor.

Question #10:

I always want to multiply a variable by ninety seven (97₁₀). Where would you find the number 97₁₀?
a) SRAM Data b) I/O Register c) Extended I/O Register d) Flash Program Memory

Answer #10:

I always want to multiply by 97₁₀, so the number would be encoded with the load instruction. Consequently, the data would be saved in Flash Program memory.

Question #11:

Once we know where the data is located we also know the addressing mode. In fact, “addressing mode” is just technical speak for saying where is the data?

If the data is located in Flash Program Memory you would use the immediate addressing mode to load it into one of our general purpose registers. Specifically, you would use the “load immediate” ldi Rd, K assembly instruction. Where ldi is a short hand way “mnemonic” of saying LoaD Immediate. The source operand is constant K (upper case K) and destination operand address Rd is the register we want to contain the constant after the instruction executes. The word “operand” is again just technical speak and based on the context may be read as the “address of the data” or simply the “data” itself. For our load immediate instruction would our constant K operand be read as “the address of the data” or simply as “data”?

Answer #11:

The constant is encoded with the instruction so the operand is the “data.”

Question #12:

If the data is located in SRAM data memory, you would use the direct addressing mode. You would also use the direct addressing mode if the data is located in the extended I/O address space. There are other addressing modes that can access, these locations within the memory address space; However, we will leave them for now. The instruction you use to load data “directly” from SRAM data memory is lds Rd, k. Where lds is a short hand way of saying LoaD from SRAM data memory. The source operand is the address k (lower case K) in data memory containing the data, and destination operand addres Rd is the register we want to contain the data after the instruction executes. For our load from SRAM data memory instruction would our constant k operand be read as “the address of the data” or simply as “data”?

Answer #12:

The source operand field encoded with the instruction contains the “address of the data.”

Question #13:

You might be surprised to learn that you use the same instruction to access SRAM data and Extended I/O registers. The only thing that is different is the address. What assembly instruction would I use to load the contents of the low order byte of the ADC register (ADCL) into general purpose register r20, and at what Extended I/O address would I find this ADC register?

Answer #13:

You would use the lds r20, ADCL assembly instruction, where the assembler would replace ADCL with the address 0x78.

Question #14:

If the data is located in our I/O address space, not the extended I/O address space, you would again use the direct addressing mode; however, this time you would use the “in” instruction. The “in” instruction is the only instruction used to directly load data from the I/O address space. Consequently, if you know the data is located in the I/O address space, you know the addressing mode (direct) and the instruction to use.

What assembly instruction would I use to read the contents of PORT D’s data direction register DDRD into general purpose register r12?

Answer #14:

Looking at the Register Summary, we find register DDRD is located at address 0x0A, so we would use the in instruction.

in r12, DDRD // Where the assembler would replace DDRD with the I/O address 0x0A.

Question #15:

What assembly instruction would I use to load the contents of variable A into general purpose register r20, and within what SRAM address range would variable A be located? Hint: the top of SRAM data memory is located at address 0x8FF.

Answer #15:

You would use the lds r20, A assembly instruction, where the assembler would replace A with the SRAM address assigned to variable A by the assembler. Because the assembler will assign variable A when the program is assembled, we only know that it will be somewhere in our SRAM memory; address space 0x0100 to 0x08FF. See Figure 7-2 Program Memory Map ATmega88PA, ATmega168PA, and ATmega328P to see why the top of memory is 0x08FF.

Question #16:

How much real SRAM data memory does the ATmega328P contain?

Answer #16:

SRAM memory is located from address 0x8FF down to 0x0100. If our memory had a base address of 0x0000 then the last address would be o0x08FF – 0x0100 = 0x07FF. Which corrsponds to a 2 K byte (where K = 2¹⁰ = 1024) or 2048₁₀ byte SRAM memory address space.

Question #17:

What assembly instruction would I use to load constant 0x80 into general purpose register r24?

Answer #17:

ldi r24, 0x80

Question #18:

As mentioned earlier, constants are encoded with the instruction itself. Because immediate instruction are encoded into one 16-bit Flash Program word there are some restrictions. First, the constant must fit within a byte (8-bits). If you are working with a number; unsigned numbers must be between 0 to 255 and signed numbers between -128 to 127. Second, to fit the 8 bit constant into the 16-bit instruction, Atmel had to limit the registers which could be used to r16 to r31. How can you work with a 16-bit constant? For example; how would you load the 16-bit constant 1234₁₆ into the r17:r16 register pair?

Answer #18:

Break the constant into a high-byte and a low-byte, assigning each to its own general purpose register. For example;

ldi r17, 0x12
ldi r16, 0x34

Question #19:

Looking at the Instruction Set Summary and specifically Data Transfer Instructions, how could you load constant 0x33 into register r8?

Answer #19:

Break the constant into a high-byte and a low-byte, assigning each to its own general purpose register. For example;

Temporarily Load the constant into one of the registers from r16 to r31 and then use the move instruction mov to copu it into the desired register. For example;

ldi r16, 0x33
mov r8, r16

Question #20:

What assembly instruction would I use to move Status Register SREG into general purpose register r27?

Answer #20:

Looking at the Register Summary, we find that SREG is located at address 0x3F, so we would use the in instruction.

in r27, SREG // Where the assembler would replace SREG with the I/O address 0x3F.

Question #21:

What assembly instruction would I use to read the PINs on PORT B into general purpose register r12?

Answer #21:

Looking at the Register Summary, we find that PINB is located at address 0x03, so we would use the in instruction.

in r12, PINB // Where the assembler would replace PINB with the I/O address 0x03.

Register – Register Instructions

Question #22:

After we have loaded the date into the general purpose registers of the AVR processor, technically known as the register file, we manipulate the data as required by the problem to be solved. This often is the easiest part of the problem within the context of a load-store architecture. This is because, RISC machines offer a wide selection of register-register instructions for solving most any problem. In addition, the names of the instructions typically provide you enough information to know which one(s) to employ to solve your problem. Later in the semester we will solve more complex problems; but, for now lets look at a few simple examples.

Variables A and B have been loaded into register r2 and r3 respectively. How would you add these two numbers together putting the sum into register r2.

Answer #22:

add r2, r3

Question #23:

Some modern RISC computers have register-register instructions containing three operand fields, with the third operand field providing the processor with the address of where the answer is to be saved. Our RISC architecture only supports up to two operand fields. This means for arithmetic or logical operations requiring two operands (A plus B), the destination operand also provides one of the numbers to be operated on. Consequently, all instructions of this type destroy one of the source registers (by writing the result to it). In the problem above the source/destination register was r2. How can you perform an arithmetic or logincal operation without destroying the value in one of your source registers?

Answer #23:

Use the mov instruction to make a copy of one of your variables.

Question #24:

Write the code needed to add r2 and r3 placing the answer in register r4.

Answer #24:

mov r4, r2

add r4, r3

Question #25:

Write the code needed to take the logical or of register r2 and r3 placing the answer in register r4.

Answer #25:

mov r4, r2

or r4, r3

Question #26:

Write the code needed to take the logical and of register r2 and r3 placing the answer in register r2.

Answer #26:

and r2, r3

Question #27:

As you can see often it is simply a matter of looking up the required arithmetic or logical instruction in the “Instruction Set Summary” and plugging it into your program.

We have a 16-bit unsigned number. The most significant 8-bits are located in register r5 and the least significant 8-bits in register r4. Another way of saying the same thing is that the register pair r5:r4 contains a 16-bit unsigned number. Given that the register pair r7:r6 holds a second 16-bit number, write the code needed to add these two 16-bit numbers together placing the result back into the register pair r5:r4. Hint: do not forget the carry from the least significant byte.

Answer #27:

add r4, r6

adc r5, r7

Storing the Answer

To be continued...

Looping Example

Design Objective

When the user presses the button, read first 3 switches (least significant), if the number is less than or equal to 5 then calculate factorial. If greater than 5 turn on decimal point. Display the least significant 4 bits of the answer.

My Design Steps

Step 1: Initialized Ports

; Disable interrupts and configure stack pointer for 328P

cli

; Initialize Switches with Pull-up resistors and Test LEDs
in    r16,DDRC       // input Port C Data Direction Register (0x07) for switches 5 to 0
cbr   r16,0b00111111 // define bits 5 to 0 as input (clear bit register)
out   DDRC,r16       // outputin    r16,PORTC      // input Port C Register (0x08) for switches 5 to 0
sbr   r16,0b00111111 // add pull-up resistors (PUR)
out   PORTC,r16      // output

in    r16,DDRD       // input Port D Data Direction Register (0x0A) for switches 7 to 6
cbr   r16,0b11000000 // define bits 7 to 6 as input (clear)
out   DDRD,r16       // output

in    r16,PORTD      // input Port D Register (0x0B) for switches 7 to 6
sbr   r16,0b11000000 // add pull-up resistors (PUR)
out   PORTD,r16      // output

; Initialize SPI Port and Test LEDs

in r16,DDRB // Input from Port B Data Direction Register (DDRB) at i/o address 0x04

sbr r16,0b00101111 // Set PB5, PB3, PB2 (SCK, MOSI, SS) and PB1, PB0 (TEST LEDs) as outputs

out DDRB,r16 // Output to Port B Data Direction Register (DDRB) at i/o address 0x04

in r16,PORTB // input Port B Register (0x05) bit 2 (SS) at i/o address 0x05

cbr r16,0b00000111 // bit 1 (TEST LED1), bit 0 (TEST LED0)

out PORTB,r16 // output

ldi r16,0b01010001 // Set SPCR Enable (SPE) bit 6, Master (MSTR) bit 4,

// clock rate fck/16 (SPR1 = 0,SPR0 = 1)

out SPCR,r16 // Output to SPI Control Register (SPCR) at i/o address 0x2c

Step 2: Turned on LED 0 to indicate initialization complete

sbi PORTB, 0 // Turn on LED 0

Step 3: Wrote code to pulse the clock

start:

cbi PORTD, 5

sbi PORTD, 5

Step 4: Read in pin waiting for the button to be pressed (Loop Example 1)

// check button

sbic PIND, 2

rjmp start

Step 5: Need to filter out Bounce (Loop Example 2)

delay_50:

ldi r16, 0 // 256

wait:

dec r16 // 1 clock cycle

brne wait // + 2 cycle if true, 1 cycles if false

// 3 cycles x 256 - 1 = 599 x 1/16 MHz = 48 usec

Maximum delay that could be generated was only 48 usec

Step 6: Added a NOP instruction, max delay was now 64 usec

Set delay for nice even number of 50 usec

delay_50:

ldi r16, 200 // 200 = 0xC8

wait:

nop // 1 clock cycle

dec r16 // 1 clock cycle

brne wait // + 2 cycle if true, 1 cycles if true

// 4 cycles x 200 - 1 = 799 x 1/16 MHz = 50 usec

Step 7: Made an outside loop of 10 (Loop Example 3)

delay_500:

ldi r17, 10

delay_50:

ldi r16, 200 // 200 = 0xC8

wait:

nop // 1 clock cycle

dec r16 // 1 clock cycle

brne wait // + 2 cycle if true, 1 cycles if true

// 4 cycles x 200 - 1 = 799 x 1/16 MHz = 50 usec

dec r17

brne delay_50 // 10 x 50 usec = 500 us (approx)

Step 8: Converted loop to a subroutine so I could change condition to button release.

; --------------------------

Delay500:

push r16

push r17

ldi r17, 10 // was 10

delay_50:

ldi r16, 200 // 200 = 0xC8

wait:

nop // 1 clock cycle

dec r16 // 1 clock cycle

brne wait // + 2 cycle if true, 1 cycles if true

// 4 cycles x 200 - 1 = 799 x 1/16 MHz = 50 usec

dec r17

brne delay_50 // 10 x 50 usec = 500 us (approx)

dec r18

brne delay_500 // 10 x 50 usec = 500 us (approx)

pop r17

pop r16

ret

Step 9: Check for button pressed and then released

start:

cbi PORTD, 5

sbi PORTD, 5

// check button down

sbic PIND, 2

rjmp start

rcall Delay500 // remove bounce

check_button:

cbi PORTD, 5

sbi PORTD, 5

// check button up

sbis PIND, 2

rjmp check_button

rcall Delay500 // remove bounce

Step 10: Read Switch and check if less than or equal to 5

in r16, PINC

cbr r16, 0b11110000 // clear undefined bits

cpi r16, 6 // no unsigned less than or equal to 5

brlo factorial

// error condition

ldi r16, 0x80 // decimal point

mov r8, r16

rcall writeDisplay

rjmp start

Step 11: Calculate Factorial (Loop Example 4)

factorial:

ldi r17, 1

mov r0, r17

calculate:

mul r0, r16 // r1:r0 = r0 x r16

dec r16

brne calculate

Step 12: Convert least significant nibble to 7-segment display (Flash Program Indirect Addressing Mode)

display_answer:

ldi r16, 0b00001111 // limit to least significant nibble

and r0, r16

ldi ZL,low(table<<1) // load address of look-up

ldi ZH,high(table<<1)

clr r1

add ZL, r0

adc ZH, r1

lpm spi7SEG, Z

rcall writeDisplay

rjmp start

// gfedcba gfedcba gfedcba gfedcba gfedcba gfedcba

table: .DB 0b00111111, 0b00000110, 0b01011011, 0b01001111, 0b01100110, 0b01101101

//          0           1           2           3           4           5

.DB 0b01111101, 0b00000111, 0b01111111, 0b01100111, 0b01110111, 0b01111100

//          6           7           8           9           A           B

.DB 0b00111001, 0b01011110, 0b01111001, 0b01110001

// C D E F

Midterm 1 Review

The midterm has not been written; however, I envision a mix of multiple choice (» 15), short answer, and Programming problems.

Material Covered in Midterm 1 (Lecture 01 to 08)

	Lecture	Worksheets
• Introduction to Assembly – Simple Programming	01
• Introduction to Microcontrollers	02
• AVR Peripherals – including AVR Studio and Simulation	From lab material
• Load-Store Programming	03	Questions on Page 9, Load-Store Worksheet
• AVR ALU and SREG	04 and	Questions on Page 11 of lecture 04
• Bit and Bit-Test Instructions	From lab material
• AVR Branching and Looping	05 and 06	AVR Branching Solutions and AVR Looping Solutions
• Quiz 1		Quiz 1 Review – Solutions
• AVR Subroutine Basics	07
• ATmega GPIO	08 and Lab material	Labs 1 and 2
• Labs up to and including Lab 2
•		Practice Programming Problems

Sample Topics

AVR Assembly: Number Systems, Instruction Types, MCU Instructions, AVR Assembly Files

AVR Microcontroller: Flip-flops and Registers, Microcontroller Architecture, CPU Operation, ISA Registers, Pipeline, Memory Mapped I/O

Load-Store Programming (plus Addressing Modes): Data Transfer Instructions, Addressing Modes, Data Transfer Instruction encoding.

ALU and SREG: ALU Instructions, SREG Bits

Bit and Bit-Test Instructions: Bit and Bit-Test Instructions, Lab

AVR Jumping, Branching, and Looping: Compare and Test Instructions, Control Transfer Instructions, Modification of ISA Registers, Instruction call, rcall, jmp, rjmp encoding, Implementation in assembly of high level programming control transfer and looping instructions, Software Timing Loops, Pipeline Operation

AVR Peripherals – including AVR Studio Assembly and Simulation: From Lab Material

You will be provided with the following

Arduino Proto‐Shield Schematic
Four (4) pages from the ATmega328P Summary (Atmel Document 8161S)
- Section 5. Register Summary Pages 10 and 11 (not 8 and 9)
- Section 6. Instruction Set Summary Pages 12 and 13 (not 14)

You can bring…

One half (½) of the front side of notes. See Syllabus for rules on what may and may not be on your sheet of notes.
4-function calculator

Midterm 2 Worksheet

Midterm II Review Questions

In addition to the following questions, I would recommend reviewing the Midterm 1 Load-Store Worksheet

Warning:

Your one-sided 8 ½ x 11 page of notes may not contain questions and answers or copy-pasted bullet-points. It may only contain technical information relevant to the ATmega processor and other coursework related material. The following questions are provided to help you prepare for the second midterm only.